(1) Field of the Invention
The invention relates to the fabrication of semiconductors, and more specifically to the method applied for localized oxidation of silicon (LOCOS).
(2) Description of the Prior Art
The most widely used method for creating isolation in NMOS and PMOS integrated circuits is the basic LOCOS structure. In the LOCOS approach, the oxide is selectively grown over the field regions of the IC. This is done by covering the active regions with a thin layer of silicon nitride. When the field oxide is grown, the active regions remain covered by nitride, which prevents oxidation of the silicon beneath. In the field regions the surface of the silicon substrate is exposed prior to field oxidation by etching away the nitride layers in these areas. In addition, the silicon in these regions is also selectively implanted at this point with the channel-stop dopant. Thus, the channel-stop regions become self-aligned to the field oxide.
If the field oxide is selectively grown without etching the silicon, the resulting field oxide will be partially recessed. If, on the other hand, the silicon is etched after the oxide-preventing layer is patterned, the field oxide can be grown until it forms a planar surface with the silicon substrate. This is known as the fully recessed isolation oxide process. In the semi-recessed process, the height of the oxide protruding above the level of the active region surface is larger than in the fully recessed process, but it is smaller than in the grow-oxide-and-etch process. In addition, the semi-recessed oxide step has a gentle slope that is more easily covered by subsequent polysilicon and metal layers.
The conventional LOCOS isolation process has a problem known as "bird's beak encroachment". Therefore, the scalability of the LOCOS is limited to about the 1 um range.
The LOCOS process than uses the property that oxygen diffuses through Si.sub.3 N.sub.4 very slowly. When silicon is covered with silicon nitride no oxide can grow. In addition, nitride itself oxidizes at a very slow rate and will thus remain as an integral oxidation barrier layer throughout the entire oxidation step.
FIG. 1 shows the major processing steps. After a wafer 10 with a bare silicon surface is cleaned, a 20 to 60 nm. layer 12 of SiO.sub.2 is thermally grown on its surface. Next, a 100 to 200 nm.-thick layer 14 of Chemical Vapor Deposition (CVD) silicon nitride Si.sub.3 Ni.sub.4, which functions as an oxidation mask, is deposited. The active regions are then defined with a photolithographic step so that they are protected by the photoresist patterns. The composite oxide/nitride layers are then plasma-etched as a stack. With the photoresist pattern in place, the wafer is subsequently implanted with a 10.sup.12 to 10.sup.13 cm.sup.-2 dose of boron with energies in the range of 60 to 100 keV. This channel stop is now self-aligned to the n-channel devices. The underlying layer of oxide within the stack, called a pad or buffer oxide, is used to cushion the transition of stresses between the silicon substrate and the nitride film.
FIG. 2 shows how, after the channel stop implant, the field oxide 20 with a thickness of 500 to 900 nm. is thermally grown by wet oxidation at temperatures of 900 to 1000 degrees C. for 4 to 8 hours.
FIG. 3 shows the next stage of the processing sequence, the masking nitride layer is stripped with phosphoric acid at 180 degrees C. using a reflux boiler. Then the pad oxide is etched (not shown).
U.S. Pat. No. 5,599,731 (Han et al.) discloses a N I/I into the pad oxide only in areas where the bird's beak will be formed.
U.S. Pat. No. 5,523,255 (Hyung et al.) shows a conventional Pad Oxide with overlying oxidation barrier layer.
U.S. Pat. No. 5,308,787 (Hong et al.) shows a nitrogen ion implant (N I/I) into the substrate in areas where the FOX is grown. The N I/I reduces the oxidation rate.
U.S. Pat. No. 5,677,234 (Koo et al.) shows a N containing layer (formed by N I/I) over the buffer layer.
U.S. Pat. No. 5,789,305 (Peidous) shows a N I/I into the substrate in bird's beak areas.